Job Details: Job Description: An STA (Static Timing Analysis) Design Intern is responsible for evaluating the timing margins of semiconductor logic designs (ASIC/SoC) to ensure the chip will function at target speeds without errors. Key tasks include running timing constraints, analyzing
Job Description Job Description · Work as part of an established EDA team to maintain, support, and enhance a production RTL-to-Gates implementation, static verification, and signoff flow · Provide hands-on support to global project teams (Europe, India,
General Information Job Title ASIC Physical Design, Sr Director in HCMC/ Da Nang Job ID 16846 Country Viet Nam City Ho Chi Minh Date Posted 06-Apr-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type
Job Details: Job Description: A Physical Design Intern assists in the semiconductor RTL-to-GDSII flow, learning to transform circuit designs into physical layouts for chip manufacturing. Interns work with senior engineers on floorplanning, placement, routing, and physical
ACG_3698_JOB Our client is a leading technology company in Vietnam who is looking for a qualified candidate to join their firm. Position Overview We are looking for a Physical Design Engineer to manage and execute the